FPGA and embedded real-time pipeline

About ASW Open R&D Internship Challenge

Africa Space Works is opening a hands-on internship challenge for students and early-career engineers who want to work on demanding space software, embedded systems, FPGA and AI problems. The program is built around practical engineering: internal repositories, cloud workspaces, selected FPGA cards, remote or office participation, weekly delivery discipline, and monthly technical reviews.

The common challenge is to build a safe test bench for a real-time camera-based tracking system. The system will use camera input, computer vision, FPGA and embedded processing, measurable validation, and controlled actuator-style outputs to detect and follow small moving targets in a controlled environment.

All tracks are connected. Track A enables execution, Track B proves performance, Track C builds the real-time hardware pipeline, and Track D builds the computer vision and AI tracking layer.

Role Overview - Track C: FPGA and Embedded Real-Time Pipeline

As an intern on Track C, you will work close to the hardware target. Your mission is to build the real-time path that connects camera input, FPGA processing, embedded control and controlled output commands.

In this challenge, the hardware target is concrete: we are building the foundations of a camera-based tracking system. The system should be able to observe a moving target inside a safe test bench, extract useful tracking signals, and generate clean commands for motor, rotor, gimbal, servo or actuator-style mechanisms that can follow the target during validation.

The goal is not to hide everything behind software. Your work should expose clear hardware interfaces, measurable latency, useful registers, documented data paths and FPGA-friendly building blocks that the other tracks can test and improve.

Key Responsibilities

• Develop board control mechanisms, firmware helpers, register interfaces, low-level drivers and communication paths.
• Integrate camera input and prepare FPGA-friendly data paths for real-time detection and tracking experiments.
• Implement or support low-latency tracking primitives such as frame differencing, thresholding, centroid extraction, bounding boxes, simple filters or trajectory features.
• Build clean interfaces between FPGA logic, embedded control code, and higher-level tracking algorithms from Track D.
• Support controlled motor, rotor, gimbal, servo, or actuator-style command interfaces for safe target-following validation.
• Collaborate with Track B to measure timing, reproducibility, failure modes and hardware-in-the-loop behavior.
• Collaborate with Track A to make the boards accessible, observable and usable in a remote or shared lab environment.
• Leave a useful daily trace (commits, debugging notes, MRs) and present progress at weekly and monthly reviews.

Requirements

• Baseline knowledge in embedded systems, FPGA architecture, hardware description languages such as VHDL, Verilog or SystemVerilog, or embedded C/C++.
• Good working knowledge of Python.
• Willingness to learn and use Rust, C and shell scripting as needed for low-level tooling, automation, drivers and hardware integration.
• Interest in camera interfaces, real-time tracking, control loops, motor/actuator control and hardware-in-the-loop testing.
• Experience or strong motivation to learn low-level hardware interfaces, registers, timing constraints, drivers and data-path design.
• Strong respect for hardware safety and controlled execution environments.
• Ability to document trade-offs clearly and make hardware systems accessible to software and computer vision teams.

Selection, Prize, and Hiring

• Fast Selection: CV screening, technical task, and interview.
• Cash Prize: Top contributors generating reproducible, integrated, and high-quality reusable engineering output may be awarded a cash prize.
• Hiring Path: The best profiles demonstrating strong technical judgment and integration skills may be offered full-time or longer-term roles at ASW.